The Deleterious Nature of Interacting Tiling Optimizations

A compiler may perform multiple optimizations, each with its own goal and cost function. While it is acknowledged that optimizations can interact, in practice the interactions are often ignored, and assumed to have no deleterious eeects. In this paper, we demonstrate for optimizations involving tiling that the interactions have unexpectedly harmful eeects on overall performance. Current trends in architecture toward multiple levels of memory and parallelism dictate that tiling be applied multiple times. Typically, each application corresponds to a given architectural feature (such as registers, cache, or instruction level or multiproces-sor parallelism), and has a speciied goal (such as increased parallelism or better locality). Compilers usually decide on some order for the multiple tiling transformations, and then independently apply them for each architectural feature. We show in three architectural scenarios that the goals of multiple applications of tiling can interact, and that a global strategy which exploits interactions can achieve better performance than multiple independent tiling decisions. We illustrate these points by considering abstractions of real application codes, giving both analysis and simulation results to support our points.